In power conversion applications, when an input power needs to be converted and transmitted over an insulation barrier to produce multiple regulated DC outputs, a cost-effective method known to the prior art is to employ a common primary switching stage to provide a switched signal to a primary side winding of a power transformer and derive multiple DC outputs from respective multiple secondary side windings. In such an approach, normally one of the DC outputs is regulated by feedback control of the primary side switching operation, while non-isolated DC to DC regulation stages are deployed for each of the remaining DC outputs, when relatively accurate voltages are required for those outputs. Alternatively, the primary side power stage can operate at a predetermined switching condition in an open loop manner, and all the DC outputs may be regulated with dedicated DC to DC post regulators.
FIG. 1 illustrates a high level schematic diagram of a multiple output power converter 10, according to the prior art. Multiple output power converter 10 comprises: a primary side control circuitry 30; a switching circuit 40, comprising an electronically controlled switch SB1 and an electronically controlled switch SB2; a primary side capacitance element CP; a transformer 50, exhibiting a primary winding 60 and a pair of secondary windings 70 and 80, magnetically coupled to primary winding 60; a pair of unidirectional electronic valves D1; a pair of unidirectional electronic valves D2; a unidirectional electronic valve D3; a unidirectional electronic valve D4; a plurality of capacitance elements C1, C2, C3 and C4; a pair of inductance elements L1 and L2; a pair of electronically controlled switches S1 and S2; a secondary side control circuitry 85; a voltage divider 90; and a reference voltage source 100.
In one embodiment, each of electronically controlled switches SB1, SB2, S1 and S2 is implemented as an n-channel field-effect-transistor (NFET), and is described herein as such. In another embodiment, each of primary side capacitance element CP and capacitance elements C1, C2, C3 and C4 is implemented as a capacitor, and is described herein as such. In one embodiment, each of pair of unidirectional electronic valves D1, pair of unidirectional electronic valves D2 and unidirectional electronic valves D3 and D4 is implemented as a diode, and is described herein as such. In another embodiment, each of inductance elements L1 and L2 is implemented as an inductor and is described herein as such. Switching circuit 40 is illustrated and described herein as comprising a half bridge circuit, however this is not meant to be limiting in any way and any appropriate type of switching circuit for providing power to primary winding 60 may be provided, including, but not limited to, a full bridge circuit, a push-pull circuit, a flyback converter circuit and a forward converter circuit.
The drain of NFET SB1 is coupled to a power terminal of a power source (not shown) and the gate of NFET SB1 is coupled to a respective output of primary side control circuitry 30. The source of NFET SB1 is coupled to a first end of primary side capacitor CP and the drain of NFET SB2. A second end of primary side capacitor CP is coupled to a first end of primary winding 60 of transformer 50. A second end of primary winding 60 is coupled to the source of NFET SB2 and the return of the power source. The gate of NFET SB2 is coupled to a respective output of primary side control circuitry 30.
A first end of secondary winding 70 is coupled to the anode of a first diode D1 and a second end of secondary winding 70 is coupled to the anode of a second diode D1. The cathode of each diode D1 is coupled to a first end of voltage divider 90 and a first end of capacitor C1, at an output VO1. Output VO1 is coupled to an associated load (not shown). A second end of capacitor C1 is coupled to a common potential and a second end of voltage divider 90 is coupled to the common potential. A dividing node of voltage divider 90 is coupled to a respective input of primary side control circuitry 30 and a positive terminal of reference voltage source 100 is coupled to a respective input of primary side control circuitry 30. A return of reference voltage source 100 and a center tap of secondary winding 70 are each coupled to the common potential.
A first end of secondary winding 80 is coupled to the anode of a first diode D2 and a second end of secondary winding 80 is coupled to the anode of a second diode D2. The cathode of each diode D2 is coupled to a first end of capacitor C2 and a drain of NFET S1. The source of NFET S1 is coupled to the cathode of diode D3 and a first end of inductor L1. A second end of inductor L1 is coupled to a first end of capacitor C3 and a respective input of secondary side control circuitry 85, at an output VO2. Output VO2 is coupled to an associated load (not shown). A second end of capacitor C2, the anode of diode D3, a second end of capacitor C3 and a center tap of secondary winding 80 are each coupled to the common potential. The gate of NFET S1 is coupled to a respective output of secondary side control circuitry 85, denoted signal VG3.
Node VO1 is further coupled to a first end of inductor L2. A second end of inductor L2 is coupled to the drain of NFET S2 and the anode of diode D4. The cathode of diode D4 is coupled to a first end of capacitor C4 and a respective input of secondary side control circuitry 85, at an output VO3. Output VO3 is coupled to an associated load (not shown). The source of NFET S2 and a second end of capacitor C4 are each coupled to the common potential. The gate of NFET S2 is coupled to a respective output of secondary side control circuitry 85, denoted signal VG4.
In operation, primary side control circuitry 30 is arranged to alternately open and close NFETs SB1 and SB2 such that primary winding 60 is charged when NFET SB1 is closed and discharged when NFET SB2 is closed. In one embodiment, the duty cycle of switching circuit 40 is adjusted responsive to the voltage at output VO1 in comparison with the voltage across reference voltage source 100. In another embodiment, switching circuit 40 operates at a fixed duty cycle of near 50%, with a variable frequency, the frequency varied responsive to the voltage at output VO1 in comparison with the voltage across reference voltage source 100. When NFET SB1 is closed, and NFET SB2 is open, primary winding 60 is charging and power is output from secondary winding 70 via first diode D1. When NFET SB2 is closed, and NFET SB is open, primary winding 60 is discharging and power is output from secondary winding 70 via second diode D1. Primary side capacitor CP ensures that the alternate charging and discharging of primary winding 60 is balanced. The rectified voltage at the cathodes of diodes D1 is supplied to the load of output VO1 and is additionally divided by voltage divider 90. The divided voltage is compared to the reference voltage output by reference voltage source 100. In the event that the divided voltage is higher than the output of reference voltage source 100, primary side control circuitry 30 is arranged to either reduce the duty cycle of switching circuit 40 or increase the switching frequency of switching circuit 40, thereby reducing the amount of power supplied via secondary winding 70. In the event that the divided voltage is lower than the output of reference voltage source 100, primary side control circuitry 30 is arranged to either increase the duty cycle of switching circuit 40 or reduce the switching frequency of switching circuit 40, thereby increasing the amount of power supplied via secondary winding 70. Capacitor C1 is arranged to smooth the voltage at output VO1.
Outputs VO2 and VO3 are similarly influenced by the control of primary side control circuitry 30. Particularly, power output from secondary winding 70 is split between output VO1 and output VO2, thus an increase in the power output via secondary winding 70 will cause an increase in the voltage of output VO3. Additionally, an increase in the duty cycle of switching circuit 40, or a reduction in the switching frequency of switching circuit 40, causes an respective increase in the power output via secondary winding 80, thereby causing an increase in the voltage of output VO2. For this reason, the voltage of each of output VO2 and output VO3 is independently controlled. Particularly, the voltage of output VO2 is controlled by the buck configuration of capacitor C2, NFET S1, diode D3 and inductor L1. When NFET S1 is closed responsive to a first state of signal VG3, output VO2 receives power from secondary winding 80 and inductor L1 is charged. When NFET S1 is opened responsive to a second stage of signal VG3, inductor L1 discharges through diode D3 and output VO2. Capacitor C3 is arranged to smooth the voltage of output VO2. Secondary side control circuitry 85 is arranged to detect the voltage at output VO2 and is further arranged to adjust the duty cycle of signal VG3 applied to the gate of NFET S1 to maintain the voltage at a predetermined value. Similarly, the voltage of output VO3 is controlled by the boost configuration of NFET S2, diode D4 and inductor L2. When NFET S2 is closed responsive to a first state of signal VG4, inductor L2 is charged from secondary winding 70. When NFET S2 is opened responsive to a second stage of signal VG4, inductor L2 discharges through diode D4 and output VO3 while additionally receiving power from secondary winding 70. Capacitor C4 is arranged to smooth the voltage of output VO3. Secondary side control circuitry 85 is arranged to detect the voltage at output VO3 and is further arranged to adjust the duty cycle of signal VG4 applied to the gate of NFET S2 to adjust the voltage at a predetermined value.
As described above, each output VO2 and VO3, and any additional outputs, need to be regulated by a respective electronically controlled switch, with an accompanying respective inductor and diode. Additionally, the buck configuration of output VO2 further requires capacitor C2. Furthermore, NFETs S1, S2 exhibit significant switching losses. Particularly, the drain-source voltage of each NFET S1, S2 equals a particular value when being switched from the open state to the closed state. Switching loss occurs under such hard switching circumstances since the discharge of the NFET capacitance is purely dissipative and produces a strong discharge current spike and associated switching noise.